Fast yield ramping shortens the cycle time from manufacturing to market. In semiconductor manufacturing challenges to fast yield ramping become more stringent because capital investments for semiconductor fabrication facilities (fabs) are sky rocketing while market demands change more rapidly and the manufacturing process, equipment, and operations become more complicated than before. The criticality of effectively managing knowledge intensive engineering analysis for fast yield ramping has grown significantly. To assist engineers in yield analysis, semiconductor fabs have adopted various platforms that provide tools for engineering data analysis (EDA).
Conventionally, triggered by a yield analysis event and an analysis objective, an engineer generates analysis objectives and a corresponding plan internally, and then selects and applies the appropriate EDA tools in sequence to perform the analysis according to the objectives plan to accomplish his/her objective. Typically, engineering experience in developing analysis plans has not been documented or if it is documented, it is documented in disparate documentation not easily reused. Engineering analysis procedures have not been systematically extracted nor stored for sharing and re-use.
Thus a disadvantage of the prior art is that the experience and knowledge of expert engineers may be lost over time and the learning curve of new engineers may be longer as a result.
Another disadvantage of the prior art methods is that experiments may be repeated because the knowledge of the experiment details and data are not adequately shared, thereby wasting resources, time and materials.
What is needed then, is mechanisms to overcome the above described shortcomings in the prior art.